1. Field of the Invention
The present invention generally relates, as is indicated, to a logic circuit. More particularly, the present invention relates to a logic circuit for high speed operation at low power supply voltage.
2. Description of the Related Art
As described in, for example, Japanese Laid-open Patent Publication No. 5-14166, increasing speed of operation has been tried in recent years by supplying a voltage higher than the power supply voltage between a gate and a source of a transistor using a capacitor. FIG. 31 is a diagram of a logic circuit of the prior art. Reference labels 3101, 3120 and 3110 designate a logic input terminal, an output terminal and a power supply for supplying a voltage of Vdd, respectively. Reference labels 3108 and 3109 designate a P-channel FET (field effect transistor) and an N-channel FET, respectively. Reference labels 3106 and 3107 designate bias power supplies for supplying a voltage of Vs. Reference labels 3102 and 3103 designate capacitors. Reference labels 3104 and 3105 designate an N-channel FET and a P-channel FET, respectively.
However, the logic circuit shown in FIG. 31 suffers from the following inherent limitations. That is to say, a leak current flows when the FETs 3108 and 3109 are in an OFF state. Furthermore, it is not possible in the prior art to sufficiently drive (i.e., overdrive) the FETs 3108 and 3109, or to sufficiently cut off the FETs 3108 and 3109 by biasing its gate with deep backward bias voltage. Therefore, the logic circuit according to the prior art results in a high dissipation power and cannot perform a high-speed operation at a low voltage.